The present application generally relates to semiconductor fabrication techniques and, in particular, techniques for fabricating FET (field effect transistor) devices.
As semiconductor manufacturing technologies continue to evolve toward smaller design rules and higher integration densities (e.g., 14 nanometers (nm) technology node and beyond), integrated circuit devices and components become increasingly smaller, creating challenges in layout formation and device optimization. Currently, FinFET technologies are typically implemented for FET fabrication, as such technologies provide effective complementary metal-oxide-semiconductor (CMOS) scaling solutions for FET fabrication at, and below, the 14 nm technology node. A FinFET device comprises a three-dimensional fin-shaped FET structure which includes at least one vertical semiconductor fin structure formed on a substrate, a gate structure formed over a portion of the vertical semiconductor fin, and source/drain regions formed from portions of the vertical semiconductor fin which extend from both sides of the gate structure. The portion of the vertical semiconductor fin that is covered by the gate structure between the source/drain regions comprises a channel region of the FinFET device. With FinFET and other types of FET devices, scaling is determined, in part, by how closely conductive source/drain and gate contacts can be formed in proximity to each other for a given layout without resulting in electrical shorts. The formation of air-gap spacers in fabricating FET devices involves first etching the original spacer with a reactive ion etching (ME) technique. However, a direct ME process could potentially damage the fin under the original spacer.